1 tm march 1997 hm-6617 2k x 8 cmos prom features ? low power standby and operating power - iccsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 a - iccop . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma at 1mhz ? fast access time . . . . . . . . . . . . . . . . . . . . . . 90/120ns ? industry standard pinout ? single 5.0v supply ? cmos/ttl compatible inputs ? high output drive . . . . . . . . . . . . . . . . 12 lsttl loads ? synchronous operation ? on-chip address latches ? separate output enable description the hm-6617 is a 16,384 bit fuse link cmos prom in a 2k word by 8-bit/word format with ?three-state? outputs. this prom is available in the standard 0.600 inch wide 24 pin sbdip, the 0.300 inch wide slimline sbdip, and the jedec standard 32 pad clcc. the hm-6617 utilizes a synchronous design technique. this includes on-chip address latches and a separate output enable control which makes this device ideal for applications utilizing recent generation microprocessors. this design technique, combined with the intersil advanced self-aligned silicon gate cmos process technology offers ultra-low standby current. low iccsb is ideal for battery applications or other systems with low power requirements. the intersil nicr fuse link technology is utilized on this and other intersil cmos proms. this gives the user a prom with permanent, stable storage characteristics over the full industrial and military temperature voltage ranges. nicr fuse technology combined with the low power characteristics of cmos provides an excellent alternative to standard bipolar proms or nmos eproms. all bits are manufactured storing a logical ?0? and can be selectively programmed for a logical ?1? at any bit location. ordering information package temp. range 90ns 120ns pkg. no. sbdip -40 o c to +85 o c hm1-6617b- 9 hm1- 6617-9 d24.6 smd# -55 o c to +125 o c 5962- 8954002ja 5962- 8954001ja d24.6 slim sbdip -40 o c to +85 o c hm6-6617b- 9 hm6- 6617-9 d24.3 smd# -55 o c to +125 o c 5962- 8954002la 5962- 8954001la d24.3 clcc -40 o c to +85 o c hm4-6617b- 9 hm4- 6617-9 j32.a smd# -55 o c to +125 o c 5962- 8954002xa 5962- 8954001xa j32.a pinouts hm-6617 (sbdip) top view hm-6617 (clcc) top view 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd v cc a9 p g a10 q7 q5 q4 q3 a8 e q6 5 6 7 8 11 10 9 13 12 27 28 29 26 25 24 23 22 21 3 2 1 4 32 31 30 16 17 18 19 20 14 15 a6 a5 a4 a3 a2 a1 a0 nc q0 q1 q2 gnd nc q3 q4 q5 v cc nc nc a7 nc nc nc a8 a9 nc g a10 e q7 q6 p pin description pin description nc no connect a0-a10 address inputs e chip enable q data output v cc power (+5v) g output enable p (note) output enable note: p should be hardwired to v cc except during programming. fn3017.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
2 functional diagram latched address register gated row decoder 16 128 x 128 matrix 128 7 7 a a e a g g a10 a9 a7 a8 a6 a5 a4 msb l latched address register a0 a1 a2 a3 gated column decoder and data output control 4 l msb lsb lsb 16 16 16 16 16 16 16 a 4 g address latches and gated decoders: gate on falling edge of g latch on falling edge of e all lines positive logic: active high a high output active three-state buffers: 8 q0 q1 q2 q3 q4 q5 q6 q7 hm-6617
3 background information programming algorithm the hm-6617 cmos prom is manufactured with all bits containing a logical zero (output low). any bit can be pro- grammed selectively to a logical one (output high) state by following the procedure shown below. to accomplish this, a programmer can be built that meets the specifications shown, or any of the approved commercial programmers can be used. programming sequence of events 1. apply a voltage of v cc1 to v cc of the prom. 2. read all fuse locations to verify that the prom is blank (output low). 3. place the prom in the initial state for programming: e = v ih , p = v ih , g = v il . 4. apply the correct binary address for the word to be pro- grammed. no inputs should be left open circuit. 5. after a delay of td, apply voltage of v il to e (pin 18) to ac- cess the addressed word. 6. the address may be held through the cycle, but must be held valid at least for a time equal to td after the falling edge of e . none of the inputs should be allowed to float to an invalid logic level. 7. after a delay of td, disable the outputs by applying a volt- age of v ih to g (pin 20). 8. after a delay of td, apply voltage of v il to p (pin 21). 9. after delay of td, raise v cc (pin 24) to vccprog with a rise time of tr. all outputs at v ih should track v cc with v cc -2.0v to v cc +0.3v. this could be accomplished by pulling outputs at v ih to v cc through pull-up resistors of value rn. 10. after a delay of td, pull the output which corresponds to the bit to be programmed to v il . only one bit should be programmed at a time. 11. after a delay of tpw, allow the output to be pulled to v ih through pull-up resistor rn. 12. after a delay of td, reduce v cc (pin 24) to v cc1 with a fall time of tf. all outputs at v ih should track v cc with v cc 2.0v to v cc +0.3v. this could be accomplished by pulling out- puts at v ih to v cc through pull-up resistors of value rn. 13. apply a voltage of v ih to p (pin 21). 14. after a delay of td, apply a voltage of v il to g (pin 20). 15. after a delay of td, examine the outputs for correct data. if any location verifies incorrectly, repeat steps 4 through 14 (attempting to program only those bits in the word which verified incorrectly) up to a maximum of eight attempts for a given word. if a word does not program within eight at- tempts, it should be considered a programming reject. 16. repeat steps 3 through 15 for all other bits to be pro- grammed in the prom. post-programming verification 17. place the prom in the post-programming verification mode: e = v ih , g = v il , p = v ih , v cc (pin 24) = v cc1 . 18. apply the correct binary address of the word to be veri- fied to the prom. 19. after a delay of td, apply a voltage of v il to e (pin 18). 20. after a delay of td, examine the outputs for correct data. if any location fails to verify correctly, the prom should be considered a programming reject. 21. repeat steps 17 through 20 for all possible programming locations post-programming read 22. apply a voltage of v cc2 = 4.0v to v cc (pin 24). 23. after a delay of td, apply a voltage of v ih to e (pin 18). 24. apply the correct binary address of the word to be read. 25. after a delay of tavel, apply a voltage of v il to e (pin 18). 26. after a delay of telqv, examine the outputs for correct data. if any location fails to verify correctly, the prom should be considered a programming reject. 27. repeat steps 23 through 26 for all address locations. 28. apply a voltage of v cc2 = 6.0v to v cc (pin 24). 29. repeat steps 23 through 26 for all address locations. hm-6617
4 programming cycle figure 1. hm-6617 programming cycle figure 2. hm-6617 post programming verify cycle tehel td verify valid programming valid td td td td tr td td tf tpw read data v cc prog v ih v il v ih v il v cc prog v ih v il v cc prog v ih v il v cc prog v cc gnd v cc prog v ih /v oh v il /v ol a e g p v cc q valid tavel tehel tehel v ih v il v ih v il 6.0v 5.0v 4.0v 0.0v v oh v ol telqv read telqv read read telqv tehel td td a e v cc q hm-6617
5 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com background information hm-6617 programming programming specifications symbol parameter min typ max units v il input ?0? 0.0 0.2 0.8 v v ih voltage ?1? (note 6) vcc-2 v cc vcc+0.3 v vccprog programming v cc (note 2) 12.0 12.0 12.5 v v cc1 operating v cc 4.5 5.5 5.5 v v cc2 special verify v cc (note 3) 4.0 - 6.0 v td delay time 1.0 1.0 - s tr rise time 1.0 10.0 10.0 s tf fall time 1.0 10.0 10.0 s tehel chip enable pulse width 50 - - ns tavel address valid to chip enable low time 20 - - ns telqv chip enable low to output valid time - - 120 ns tpw programming pulse width (note 4) 90 100 110 s tip input leakage at v cc = vccprog -10 +1.0 10 a iop data output current at v cc = vccprog - -5.0 -10 ma rn output pull-up resistor (note 5) 5 10 15 k ? t a ambient temperature - 25 - o c notes: 1. all inputs must track v cc (pin 24) within these limits. 2. vccprog must be capable of supplying 500ma. 3. see steps 22 through 29 of the programming algorithm. 4. see step 11 of the programming algorithm. 5. all outputs should be pulled up to v cc through a resistor of value rn. 6. except during programming (see programming cycle waveforms). hm-6617
6 absolute maximum ratings thermal information supply voltage (all voltages reference to device gnd) . . . . +7.0v input or output voltage applied for all grades . . . . . . gnd -0.3v to v cc +0.3v typical derating factor . . . . . . . . . . . 5ma/mhz increase in iccop esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions operating voltage range . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v operating temperature range: hm-6617-9, b-9 . . . -40 o c to +85 o c thermal resistance (typical) ja jc sbdip package. . . . . . . . . . . . . . . . . . 48 o c/w 9 o c/w slim sbdip . . . . . . . . . . . . . . . . . . . . . 65 o c/w 14 o c/w clcc package . . . . . . . . . . . . . . . . . . 58 o c/w 19 o c/w maximum storage temperature range . . . . . . . . .-65 o c to +150 o c maximum junction temperature. . . . . . . . . . . . . . . . . . . . . . +175 o c maximum lead temperature (soldering 10s). . . . . . . . . . . . +300 o c die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5473 gates caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not i mplied. dc electrical specifications v cc = 5v 10%; (hm-6617b-9, hm-6617-9) symbol parameter min max units test conditions v ih logical one input voltage 2.4 vcc+0.3 v v cc = 5.5v v il logical zero input voltage -0.3 0.8 v v cc = 4.5v voh1 logical one output voltage 2.4 - v i oh = -2.0ma, v cc = 4.5v voh2 logical one output voltage (note 2) vcc-1.0 - v i oh = -100 a, v cc = 4.5v vol logical zero output voltage - 0.4 v i ol = +4.8ma, v cc = 4.5v ii input leakage -1.0 +1.0 av in = v cc or gnd, v cc = 5.5v ioz output leakage -1.0 +1.0 av o = v cc or gnd, g = v cc , v cc = 5.5v iccsb standby power supply current - 100 av in = v cc or gnd, v cc = 5.5v, i o = 0 iccop operating power supply current (note 3) - 20 ma f = 1mhz, v cc = 5.5v, i o = 0, v in = v cc or gnd ac electrical specifications symbol parameter hm-6617b-9 hm-6617-9 units test conditions min max min max (1) tavqv address access time - 105 - 140 ns (notes 1, 4) (2) telqv chip enable access time - 90 - 120 ns (notes 1, 4) (3) telqx chip enable time 5 - 5 - ns (notes 2, 4) (4) tavel address setup time 15 - 20 - ns (notes 1, 4) (5) telax address hold time 20 - 25 - ns (notes 1, 4) (6) teleh chip enable low width 95 - 120 - ns (notes 1, 4) (7) tehel chip enable high width 40 - 40 - ns (notes 1, 4) (8) telel cycle time 136 - 160 - ns (notes 1, 4) (9) tglqv output access time - 40 - 50 ns (notes 1, 4) (10) tglqx output enable time 5 - 5 - ns (notes 2, 4) (11) tghqz output disable time - 40 - 50 ns (notes 2, 4) (12) tehqz chip enable disable time - 45 - 50 ns (notes 2, 4) hm-6617
7 capacitance t a = +25 o c symbol parameter max units test conditions cin input capacitance (note 2) 10 pf f = 1mhz, all measurement are referenced to device gnd cout output capacitance (note 2) 12 pf f = 1mhz, all measurement are referenced to device gnd notes: 1. input pulse levels: 0 to 3.0v; input rise and fall times: 5ns (max); input and output timing reference level: 1.5v; output load : 1 ttl gate equivalent c l = 50pf (min) - for c l greater than 50pf, access time is derated by 0.15ns per pf. 2. tested at initial design and after major design changes. 3. typical derating 5ma/mhz increase in iccop. 4. v cc = 4.5v and 5.5v. switching waveforms figure 3. read cycle tavqv (1) telel (8) teleh (6) tavel (4) tehel (7) telqx (3) tghqz (11) tehqz (12) (10) tglqx telqv (2) tglqv (9) telax addresses e g data 1.5v 1.5v 1.5v 1.5v 3.0v 0v 3.0v 0v 3.0v 0v t s 1.5v addresses valid data valid address valid 1.5v 1.5v (5) output q0-q7 1.5v test circuit figure 4. test circuit dut equivalent circuit 1.5v i ol i oh c l test head capacitance (note) note: hm-6617
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